STLdoc
STLdocumentation
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros
armintr.h
Go to the documentation of this file.
1 /***
2 * armintr.h - definitions and declarations for ARM specific intrinsics
3 *
4 * Copyright (c) Microsoft Corporation. All rights reserved.
5 *
6 *Purpose:
7 * This file contains constant definitions and external subroutine
8 * declarations for the ARM specific intriniscs
9 *
10 ****/
11 
12 #pragma once
13 
14 
15 #if !defined (_M_ARM)
16 #error This header is specific to ARM targets
17 #endif /* !defined (_M_ARM) */
18 
19 
20 #if defined (__cplusplus)
21 extern "C" {
22 #endif /* defined (__cplusplus) */
23 
25 {
26  _ARM_LSR = 0,
27  _ARM_LSL = 1,
28  _ARM_ASR = 2,
30 }
32 
33  int __arm_gen_s_Rd_Rd (const unsigned int, int);
34  int __arm_gen_s_Rd_RdRn (const unsigned int, int, int);
35  int __arm_gen_s_Rd_RdRm (const unsigned int, int, int);
36  int __arm_gen_s_Rd_RnRm_g (const unsigned int, int, int);
37  int __arm_gen_s_Rd_RnRm_q (const unsigned int, int, int);
38  int __arm_gen_s_Rd_Rn (const unsigned int, int);
39  int __arm_gen_s_Rd_Rn_q (const unsigned int, int);
40  int __arm_gen_s_Rd_RnRm (const unsigned int, int, int);
41  int __arm_gen_s_Rd_Rm (const unsigned int, int);
42  int __arm_gen_s_Rd_Rm_q (const unsigned int, int);
43  int __arm_gen_s_Rd_Rm2 (const unsigned int, int);
44  __int64 __arm_gen_s_Rdn_RdnRmRs(const unsigned int, __int64, int, int);
45  __int64 __arm_gen_s_Rdn_RmRs (const unsigned int, int, int);
46  int __arm_gen_s_Rn_RmRs (const unsigned int, int, int);
47  int __arm_gen_s_Rn_RmRsRd (const unsigned int, int, int, int);
48 unsigned int __arm_gen_u_Rd_Rd (const unsigned int, unsigned int);
49 unsigned int __arm_gen_u_Rd_RdRn (const unsigned int, unsigned int, unsigned int);
50 unsigned int __arm_gen_u_Rd_RdRm (const unsigned int, unsigned int, unsigned int);
51 unsigned int __arm_gen_u_Rd_RnRm_g (const unsigned int, unsigned int, unsigned int);
52 unsigned int __arm_gen_u_Rd_Rn (const unsigned int, unsigned int);
53 unsigned int __arm_gen_u_Rd_RnRm (const unsigned int, unsigned int, unsigned int);
54 unsigned int __arm_gen_u_Rd_Rm (const unsigned int, unsigned int);
55 unsigned int __arm_gen_u_Rd_Rm2 (const unsigned int, unsigned int);
56 unsigned __int64 __arm_gen_u_Rdn_RdnRmRs(const unsigned int, unsigned __int64, unsigned int, unsigned int);
57 unsigned __int64 __arm_gen_u_Rdn_RmRs (const unsigned int, unsigned int, unsigned int);
58 unsigned int __arm_gen_u_Rn_RmRs (const unsigned int, unsigned int, unsigned int);
59 unsigned int __arm_gen_u_Rn_RmRsRd (const unsigned int, unsigned int, unsigned int, unsigned int);
60 
61 #define _ARMINTR_ASSERT(exp, msg) __static_assert(exp, msg)
62 
63 #define _ARMINTR_IN_RANGE(val, low, high) (((val) >= low) && ((val) <= high))
64 
65 #define _ARMINTR_ASSERT_RANGE(val, low, high, name) \
66  (_ARMINTR_ASSERT(_ARMINTR_IN_RANGE((val), (low), (high)), name " is out of range '" #low " - " #high "'"))
67 #define _ARMINTR_ASSERT_ROT(rot) \
68  (_ARMINTR_ASSERT(((rot) & ~0x18U) == 0, "rotation must be 0, 8, 16, or 24"))
69 #define _ARMINTR_ASSERT_SAT_BIT(sat_bit, low, high) \
70  (_ARMINTR_ASSERT_RANGE((sat_bit), low, high, "saturation bit position")) // low, high intentionally not in (parentheses)
71 
72 #if defined (_M_THUMB)
73 #define _ARMINTR_ASSERT_SAT_SHIFT(type, amt) \
74  (_ARMINTR_ASSERT(((type) == _ARM_LSL) || ((type) == _ARM_ASR), "shift type must be _ARM_LSL or _ARM_ASR"), \
75  _ARMINTR_ASSERT(((type) != _ARM_LSL) || _ARMINTR_IN_RANGE((amt), 0, 31), "shift is out of range '0 - 31'"), \
76  _ARMINTR_ASSERT(((type) != _ARM_ASR) || _ARMINTR_IN_RANGE((amt), 1, 31), "shift is out of range '1 - 31'"))
77 
78 #else /* defined (_M_THUMB) */
79 #define _ARMINTR_ASSERT_SAT_SHIFT(type, amt) \
80  (_ARMINTR_ASSERT(((type) == _ARM_LSL) || ((type) == _ARM_ASR), "shift type must be _ARM_LSL or _ARM_ASR"), \
81  _ARMINTR_ASSERT(((type) != _ARM_LSL) || _ARMINTR_IN_RANGE((amt), 0, 31), "shift is out of range '0 - 31'"), \
82  _ARMINTR_ASSERT(((type) != _ARM_ASR) || _ARMINTR_IN_RANGE((amt), 1, 32), "shift is out of range '1 - 32'"))
83 #endif /* defined (_M_THUMB) */
84 
85 #if defined (_M_THUMB)
86 
87 #define _ARMINTR_ENCODE_XTROT(rot) (((rot) & 0x18U) << 17)
88 #define _ARMINTR_ENCODE_PKHSHIFT(shift) ((((shift) & 0x1CU) << 26) | (((shift) & 0x3U) << 22))
89 #define _ARMINTR_ENCODE_IMM5_16(imm) (((imm) & 0x1FU) << 16)
90 #define _ARMINTR_ENCODE_IMM5_7(imm) ((((imm) & 0x1CU) << 26) | (((imm) & 0x3U) << 22))
91 #define _ARMINTR_ENCODE_SAT_SH(type, amt) ((((type) & 2U) << 4) | _ARMINTR_ENCODE_IMM5_7(amt))
92 #define _ARMINTR_ENCODE_IMM4_16(bit) (((bit) & 0xFU) << 16)
93 
94 #define _ARMINTR_BFC 0x0000F36FU
95 #define _ARMINTR_BFI 0x0000F360U
96 #define _ARMINTR_SBFX 0x0000F340U
97 #define _ARMINTR_UBFX 0x0000F3C0U
98 #define _ARMINTR_QADD 0xF080FA80U
99 #define _ARMINTR_QDADD 0xF090FA80U
100 #define _ARMINTR_QDSUB 0xF0B0FA80U
101 #define _ARMINTR_QSUB 0xF0A0FA80U
102 #define _ARMINTR_QADD16 0xF010FA90U
103 #define _ARMINTR_QADD8 0xF010FA80U
104 #define _ARMINTR_QASX 0xF010FAA0U
105 #define _ARMINTR_QSAX 0xF010FAE0U
106 #define _ARMINTR_QSUB16 0xF010FAD0U
107 #define _ARMINTR_QSUB8 0xF010FAC0U
108 #define _ARMINTR_SHADD16 0xF020FA90U
109 #define _ARMINTR_SHADD8 0xF020FA80U
110 #define _ARMINTR_SHASX 0xF020FAA0U
111 #define _ARMINTR_SHSAX 0xF020FAE0U
112 #define _ARMINTR_SHSUB16 0xF020FAD0U
113 #define _ARMINTR_SHSUB8 0xF020FAC0U
114 #define _ARMINTR_UHADD16 0xF060FA90U
115 #define _ARMINTR_UHADD8 0xF060FA80U
116 #define _ARMINTR_UHASX 0xF060FAA0U
117 #define _ARMINTR_UHSAX 0xF060FAE0U
118 #define _ARMINTR_UHSUB16 0xF060FAD0U
119 #define _ARMINTR_UHSUB8 0xF060FAC0U
120 #define _ARMINTR_UQADD16 0xF050FA90U
121 #define _ARMINTR_UQADD8 0xF050FA80U
122 #define _ARMINTR_UQASX 0xF050FAA0U
123 #define _ARMINTR_UQSAX 0xF050FAE0U
124 #define _ARMINTR_UQSUB16 0xF050FAD0U
125 #define _ARMINTR_UQSUB8 0xF050FAC0U
126 #define _ARMINTR_SXTAB 0xF080FA40U
127 #define _ARMINTR_SXTAB16 0xF080FA20U
128 #define _ARMINTR_SXTAH 0xF080FA00U
129 #define _ARMINTR_UXTAB 0xF080FA50U
130 #define _ARMINTR_UXTAB16 0xF080FA30U
131 #define _ARMINTR_UXTAH 0xF080FA10U
132 #define _ARMINTR_SXTB 0xF080FA4FU
133 #define _ARMINTR_SXTB16 0xF080FA2FU
134 #define _ARMINTR_SXTH 0xF080FA0FU
135 #define _ARMINTR_UXTB 0xF080FA5FU
136 #define _ARMINTR_UXTB16 0xF080FA3FU
137 #define _ARMINTR_UXTBH 0xF080FA1FU
138 #define _ARMINTR_PKHBT 0x0000EAC0U
139 #define _ARMINTR_PKHTB 0x0020EAC0U
140 #define _ARMINTR_USAD8 0xF000FB70U
141 #define _ARMINTR_USADA8 0x0000FB70U
142 #define _ARMINTR_SADD16 0xF000FA90U
143 #define _ARMINTR_SADD8 0xF000FA80U
144 #define _ARMINTR_SASX 0xF000FAA0U
145 #define _ARMINTR_SSAX 0xF000FAE0U
146 #define _ARMINTR_SSUB16 0xF000FAD0U
147 #define _ARMINTR_SSUB8 0xF000FAC0U
148 #define _ARMINTR_UADD16 0xF040FA90U
149 #define _ARMINTR_UADD8 0xF040FA80U
150 #define _ARMINTR_UASX 0xF040FAA0U
151 #define _ARMINTR_USAX 0xF040FAE0U
152 #define _ARMINTR_USUB16 0xF040FAD0U
153 #define _ARMINTR_USUB8 0xF040FAC0U
154 #define _ARMINTR_SSAT 0x0000F300U
155 #define _ARMINTR_USAT 0x0000F380U
156 #define _ARMINTR_SSAT16 0x0000F320U
157 #define _ARMINTR_USAT16 0x0000F3A0U
158 #define _ARMINTR_CLZ 0xF080FAB0U
159 #define _ARMINTR_RBIT 0xF0A0FA90U
160 #define _ARMINTR_REV 0xF080FA90U
161 #define _ARMINTR_REV16 0xF090FA90U
162 #define _ARMINTR_REVSH 0xF0B0FA90U
163 #define _ARMINTR_SMLAD 0x0000FB20U
164 #define _ARMINTR_SMLADX 0x0010FB20U
165 #define _ARMINTR_SMLSD 0x0000FB40U
166 #define _ARMINTR_SMLSDX 0x0010FB40U
167 #define _ARMINTR_SMMLA 0x0000FB50U
168 #define _ARMINTR_SMMLAR 0x0010FB50U
169 #define _ARMINTR_SMMLS 0x0000FB60U
170 #define _ARMINTR_SMMLSR 0x0010FB60U
171 #define _ARMINTR_SMLABB 0x0000FB10U
172 #define _ARMINTR_SMLABT 0x0010FB10U
173 #define _ARMINTR_SMLATB 0x0020FB10U
174 #define _ARMINTR_SMLATT 0x0030FB10U
175 #define _ARMINTR_SMLAWB 0x0000FB30U
176 #define _ARMINTR_SMLAWT 0x0010FB30U
177 #define _ARMINTR_SMULWB 0xF000FB30U
178 #define _ARMINTR_SMULWT 0xF010FB30U
179 #define _ARMINTR_SMULBB 0xF000FB10U
180 #define _ARMINTR_SMULBT 0xF010FB10U
181 #define _ARMINTR_SMULTB 0xF020FB10U
182 #define _ARMINTR_SMULTT 0xF030FB10U
183 #define _ARMINTR_SMULL 0x0000FB80U
184 #define _ARMINTR_SMMUL 0xF000FB50U
185 #define _ARMINTR_SMMULR 0xF010FB50U
186 #define _ARMINTR_SMUAD 0xF000FB20U
187 #define _ARMINTR_SMUADX 0xF010FB20U
188 #define _ARMINTR_SMUSD 0xF000FB40U
189 #define _ARMINTR_SMUSDX 0xF010FB40U
190 #define _ARMINTR_SMLALBB 0x0080FBC0U
191 #define _ARMINTR_SMLALBT 0x0090FBC0U
192 #define _ARMINTR_SMLALTB 0x00A0FBC0U
193 #define _ARMINTR_SMLALTT 0x00B0FBC0U
194 #define _ARMINTR_SMLALD 0x00C0FBC0U
195 #define _ARMINTR_SMLALDX 0x00D0FBC0U
196 #define _ARMINTR_SMLSLD 0x00C0FBD0U
197 #define _ARMINTR_SMLSLDX 0x00D0FBD0U
198 #define _ARMINTR_SMLAL 0x0000FBC0U
199 #define _ARMINTR_UMLAL 0x0000FBE0U
200 #define _ARMINTR_UMAAL 0x0060FBE0U
201 #define _ARMINTR_UMULL 0x0000FBA0U
202 #define _ARMINTR_SDIV 0xF0F0FB90U
203 #define _ARMINTR_UDIV 0xF0F0FBB0U
204 
205 #define _ARMINTR_U_DDMx __arm_gen_u_Rd_RdRn
206 #define _ARMINTR_U_DMx __arm_gen_u_Rd_Rn
207 #define _ARMINTR_S_DMx __arm_gen_s_Rd_Rn
208 
209 #else /* defined (_M_THUMB) */
210 
211 #define _ARMINTR_ENCODE_XTROT(rot) (((rot) & 0x18U) << 7)
212 #define _ARMINTR_ENCODE_PKHSHIFT(shift) (((shift) & 0x1FU) << 7)
213 #define _ARMINTR_ENCODE_IMM5_16(imm) (((imm) & 0x1FU) << 16)
214 #define _ARMINTR_ENCODE_IMM5_7(imm) (((imm) & 0x1FU) << 7)
215 #define _ARMINTR_ENCODE_SAT_SH(type, amt) ((((type) & 2U) << 5) | _ARMINTR_ENCODE_IMM5_7(amt))
216 #define _ARMINTR_ENCODE_IMM4_16(bit) (((bit) & 0xFU) << 16)
217 
218 #define _ARMINTR_BFC 0x07C0001FU
219 #define _ARMINTR_BFI 0x07C00010U
220 #define _ARMINTR_SBFX 0x07A00050U
221 #define _ARMINTR_UBFX 0x07E00050U
222 #define _ARMINTR_QADD 0x01000050U
223 #define _ARMINTR_QDADD 0x01400050U
224 #define _ARMINTR_QDSUB 0x01600050U
225 #define _ARMINTR_QSUB 0x01200050U
226 #define _ARMINTR_QADD16 0x06200F10U
227 #define _ARMINTR_QADD8 0x06200F90U
228 #define _ARMINTR_QASX 0x06200F30U
229 #define _ARMINTR_QSAX 0x06200F50U
230 #define _ARMINTR_QSUB16 0x06200F70U
231 #define _ARMINTR_QSUB8 0x06200FF0U
232 #define _ARMINTR_SHADD16 0x06300F10U
233 #define _ARMINTR_SHADD8 0x06300F90U
234 #define _ARMINTR_SHASX 0x06300F30U
235 #define _ARMINTR_SHSAX 0x06300F50U
236 #define _ARMINTR_SHSUB16 0x06300F70U
237 #define _ARMINTR_SHSUB8 0x06300FF0U
238 #define _ARMINTR_UHADD16 0x06700F10U
239 #define _ARMINTR_UHADD8 0x06700F90U
240 #define _ARMINTR_UHASX 0x06700F30U
241 #define _ARMINTR_UHSAX 0x06700F50U
242 #define _ARMINTR_UHSUB16 0x06700F70U
243 #define _ARMINTR_UHSUB8 0x06700FF0U
244 #define _ARMINTR_UQADD16 0x06600F10U
245 #define _ARMINTR_UQADD8 0x06600F90U
246 #define _ARMINTR_UQASX 0x06600F30U
247 #define _ARMINTR_UQSAX 0x06600F50U
248 #define _ARMINTR_UQSUB16 0x06600F70U
249 #define _ARMINTR_UQSUB8 0x06600FF0U
250 #define _ARMINTR_SXTAB 0x06A00070U
251 #define _ARMINTR_SXTAB16 0x06800070U
252 #define _ARMINTR_SXTAH 0x06B00070U
253 #define _ARMINTR_UXTAB 0x06E00070U
254 #define _ARMINTR_UXTAB16 0x06C00070U
255 #define _ARMINTR_UXTAH 0x06F00070U
256 #define _ARMINTR_SXTB 0x06AF0070U
257 #define _ARMINTR_SXTB16 0x068F0070U
258 #define _ARMINTR_SXTH 0x06BF0070U
259 #define _ARMINTR_UXTB 0x06EF0070U
260 #define _ARMINTR_UXTB16 0x06CF0070U
261 #define _ARMINTR_UXTBH 0x06FF0070U
262 #define _ARMINTR_PKHBT 0x06800010U
263 #define _ARMINTR_PKHTB 0x06800050U
264 #define _ARMINTR_USAD8 0x0780F010U
265 #define _ARMINTR_USADA8 0x07800010U
266 #define _ARMINTR_SADD16 0x06100F10U
267 #define _ARMINTR_SADD8 0x06100F90U
268 #define _ARMINTR_SASX 0x06100F30U
269 #define _ARMINTR_SSAX 0x06100F50U
270 #define _ARMINTR_SSUB16 0x06100F70U
271 #define _ARMINTR_SSUB8 0x06100FF0U
272 #define _ARMINTR_UADD16 0x06500F10U
273 #define _ARMINTR_UADD8 0x06500F90U
274 #define _ARMINTR_UASX 0x06500F30U
275 #define _ARMINTR_USAX 0x06500F50U
276 #define _ARMINTR_USUB16 0x06500F70U
277 #define _ARMINTR_USUB8 0x06500FF0U
278 #define _ARMINTR_SSAT 0x06A00010U
279 #define _ARMINTR_USAT 0x06E00010U
280 #define _ARMINTR_SSAT16 0x06A00F30U
281 #define _ARMINTR_USAT16 0x06E00F30U
282 #define _ARMINTR_CLZ 0x016F0F10U
283 #define _ARMINTR_RBIT 0x06FF0F30U
284 #define _ARMINTR_REV 0x06BF0F30U
285 #define _ARMINTR_REV16 0x06BF0FB0U
286 #define _ARMINTR_REVSH 0x06FF0FB0U
287 #define _ARMINTR_SMLAD 0x07000010U
288 #define _ARMINTR_SMLADX 0x07000030U
289 #define _ARMINTR_SMLSD 0x07000050U
290 #define _ARMINTR_SMLSDX 0x07000070U
291 #define _ARMINTR_SMMLA 0x07500010U
292 #define _ARMINTR_SMMLAR 0x07500030U
293 #define _ARMINTR_SMMLS 0x075000D0U
294 #define _ARMINTR_SMMLSR 0x075000F0U
295 #define _ARMINTR_SMLABB 0x01000080U
296 #define _ARMINTR_SMLABT 0x010000C0U
297 #define _ARMINTR_SMLATB 0x010000A0U
298 #define _ARMINTR_SMLATT 0x010000E0U
299 #define _ARMINTR_SMLAWB 0x01200080U
300 #define _ARMINTR_SMLAWT 0x012000C0U
301 #define _ARMINTR_SMULWB 0x012000A0U
302 #define _ARMINTR_SMULWT 0x012000E0U
303 #define _ARMINTR_SMULBB 0x01600080U
304 #define _ARMINTR_SMULBT 0x016000C0U
305 #define _ARMINTR_SMULTB 0x016000A0U
306 #define _ARMINTR_SMULTT 0x016000E0U
307 #define _ARMINTR_SMULL 0x00C00090U
308 #define _ARMINTR_SMMUL 0x0750F010U
309 #define _ARMINTR_SMMULR 0x0750F030U
310 #define _ARMINTR_SMUAD 0x0700F010U
311 #define _ARMINTR_SMUADX 0x0700F030U
312 #define _ARMINTR_SMUSD 0x0700F050U
313 #define _ARMINTR_SMUSDX 0x0700F070U
314 #define _ARMINTR_SMLALBB 0x01400080U
315 #define _ARMINTR_SMLALBT 0x014000C0U
316 #define _ARMINTR_SMLALTB 0x014000A0U
317 #define _ARMINTR_SMLALTT 0x014000E0U
318 #define _ARMINTR_SMLALD 0x07400010U
319 #define _ARMINTR_SMLALDX 0x07400030U
320 #define _ARMINTR_SMLSLD 0x07400050U
321 #define _ARMINTR_SMLSLDX 0x07400070U
322 #define _ARMINTR_SMLAL 0x00E00090U
323 #define _ARMINTR_UMLAL 0x00A00090U
324 #define _ARMINTR_UMAAL 0x00400090U
325 #define _ARMINTR_UMULL 0x00800090U
326 
327 #define _ARMINTR_U_DDMx __arm_gen_u_Rd_RdRm
328 #define _ARMINTR_U_DMx __arm_gen_u_Rd_Rm
329 #define _ARMINTR_S_DMx __arm_gen_s_Rd_Rm
330 
331 #endif /* defined (_M_THUMB) */
332 
333 
334 /* ARMv4 */
335 
336 #define _arm_smlal(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLAL, (_RdHiLo), (_Rn), (_Rm)))
337 #define _arm_umlal(_RdHiLo, _Rn, _Rm) (__arm_gen_u_Rdn_RdnRmRs(_ARMINTR_UMLAL, (_RdHiLo), (_Rn), (_Rm)))
338 
339 /* ARMv5E */
340 
341 #define _arm_clz(_Rm) (__arm_gen_u_Rd_Rm2(_ARMINTR_CLZ, (_Rm)))
342 
343 #define _arm_qadd(_Rm, _Rn) (__arm_gen_s_Rd_RnRm_q(_ARMINTR_QADD, (_Rn), (_Rm)))
344 #define _arm_qdadd(_Rm, _Rn) (__arm_gen_s_Rd_RnRm_q(_ARMINTR_QDADD, (_Rn), (_Rm)))
345 #define _arm_qdsub(_Rm, _Rn) (__arm_gen_s_Rd_RnRm_q(_ARMINTR_QDSUB, (_Rn), (_Rm)))
346 #define _arm_qsub(_Rm, _Rn) (__arm_gen_s_Rd_RnRm_q(_ARMINTR_QSUB, (_Rn), (_Rm)))
347 
348 #define _arm_smlabb(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLABB, (_Rn), (_Rm), (_Ra)))
349 #define _arm_smlabt(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLABT, (_Rn), (_Rm), (_Ra)))
350 #define _arm_smlatb(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLATB, (_Rn), (_Rm), (_Ra)))
351 #define _arm_smlatt(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLATT, (_Rn), (_Rm), (_Ra)))
352 
353 #define _arm_smlalbb(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLALBB, (_RdHiLo), (_Rn), (_Rm)))
354 #define _arm_smlalbt(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLALBT, (_RdHiLo), (_Rn), (_Rm)))
355 #define _arm_smlaltb(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLALTB, (_RdHiLo), (_Rn), (_Rm)))
356 #define _arm_smlaltt(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLALTT, (_RdHiLo), (_Rn), (_Rm)))
357 
358 #define _arm_smlawb(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLAWB, (_Rn), (_Rm), (_Ra)))
359 #define _arm_smlawt(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLAWT, (_Rn), (_Rm), (_Ra)))
360 
361 #define _arm_smulbb(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMULBB, (_Rn), (_Rm)))
362 #define _arm_smulbt(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMULBT, (_Rn), (_Rm)))
363 #define _arm_smultb(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMULTB, (_Rn), (_Rm)))
364 #define _arm_smultt(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMULTT, (_Rn), (_Rm)))
365 
366 #define _arm_smulwb(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMULWB, (_Rn), (_Rm)))
367 #define _arm_smulwt(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMULWT, (_Rn), (_Rm)))
368 
369 /* ARMv6 */
370 
371 #define _arm_sadd16(_Rn, _Rm) (__arm_gen_s_Rd_RnRm_g(_ARMINTR_SADD16, (_Rn), (_Rm)))
372 #define _arm_sadd8(_Rn, _Rm) (__arm_gen_s_Rd_RnRm_g(_ARMINTR_SADD8, (_Rn), (_Rm)))
373 #define _arm_sasx(_Rn, _Rm) (__arm_gen_s_Rd_RnRm_g(_ARMINTR_SASX, (_Rn), (_Rm)))
374 #define _arm_ssax(_Rn, _Rm) (__arm_gen_s_Rd_RnRm_g(_ARMINTR_SSAX, (_Rn), (_Rm)))
375 #define _arm_ssub16(_Rn, _Rm) (__arm_gen_s_Rd_RnRm_g(_ARMINTR_SSUB16, (_Rn), (_Rm)))
376 #define _arm_ssub8(_Rn, _Rm) (__arm_gen_s_Rd_RnRm_g(_ARMINTR_SSUB8, (_Rn), (_Rm)))
377 
378 #define _arm_shadd16(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SHADD16, (_Rn), (_Rm)))
379 #define _arm_shadd8(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SHADD8, (_Rn), (_Rm)))
380 #define _arm_shasx(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SHASX, (_Rn), (_Rm)))
381 #define _arm_shsax(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SHSAX, (_Rn), (_Rm)))
382 #define _arm_shsub16(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SHSUB16, (_Rn), (_Rm)))
383 #define _arm_shsub8(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SHSUB8, (_Rn), (_Rm)))
384 
385 #define _arm_qadd16(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_QADD16, (_Rn), (_Rm)))
386 #define _arm_qadd8(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_QADD8, (_Rn), (_Rm)))
387 #define _arm_qasx(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_QASX, (_Rn), (_Rm)))
388 #define _arm_qsax(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_QSAX, (_Rn), (_Rm)))
389 #define _arm_qsub16(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_QSUB16, (_Rn), (_Rm)))
390 #define _arm_qsub8(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_QSUB8, (_Rn), (_Rm)))
391 
392 #define _arm_uadd16(_Rn, _Rm) (__arm_gen_u_Rd_RnRm_g(_ARMINTR_UADD16, (_Rn), (_Rm)))
393 #define _arm_uadd8(_Rn, _Rm) (__arm_gen_u_Rd_RnRm_g(_ARMINTR_UADD8, (_Rn), (_Rm)))
394 #define _arm_uasx(_Rn, _Rm) (__arm_gen_u_Rd_RnRm_g(_ARMINTR_UASX, (_Rn), (_Rm)))
395 #define _arm_usax(_Rn, _Rm) (__arm_gen_u_Rd_RnRm_g(_ARMINTR_USAX, (_Rn), (_Rm)))
396 #define _arm_usub16(_Rn, _Rm) (__arm_gen_u_Rd_RnRm_g(_ARMINTR_USUB16, (_Rn), (_Rm)))
397 #define _arm_usub8(_Rn, _Rm) (__arm_gen_u_Rd_RnRm_g(_ARMINTR_USUB8, (_Rn), (_Rm)))
398 
399 #define _arm_uhadd16(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UHADD16, (_Rn), (_Rm)))
400 #define _arm_uhadd8(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UHADD8, (_Rn), (_Rm)))
401 #define _arm_uhasx(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UHASX, (_Rn), (_Rm)))
402 #define _arm_uhsax(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UHSAX, (_Rn), (_Rm)))
403 #define _arm_uhsub16(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UHSUB16, (_Rn), (_Rm)))
404 #define _arm_uhsub8(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UHSUB8, (_Rn), (_Rm)))
405 
406 #define _arm_uqadd16(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UQADD16, (_Rn), (_Rm)))
407 #define _arm_uqadd8(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UQADD8, (_Rn), (_Rm)))
408 #define _arm_uqasx(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UQASX, (_Rn), (_Rm)))
409 #define _arm_uqsax(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UQSAX, (_Rn), (_Rm)))
410 #define _arm_uqsub16(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UQSUB16, (_Rn), (_Rm)))
411 #define _arm_uqsub8(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UQSUB8, (_Rn), (_Rm)))
412 
413 #define _arm_sxtab(_Rn, _Rm, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_s_Rd_RnRm(_ARMINTR_SXTAB | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn), (_Rm)))
414 #define _arm_sxtab16(_Rn, _Rm, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_s_Rd_RnRm(_ARMINTR_SXTAB16 | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn), (_Rm)))
415 #define _arm_sxtah(_Rn, _Rm, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_s_Rd_RnRm(_ARMINTR_SXTAH | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn), (_Rm)))
416 
417 #define _arm_uxtab(_Rn, _Rm, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_u_Rd_RnRm(_ARMINTR_UXTAB | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn), (_Rm)))
418 #define _arm_uxtab16(_Rn, _Rm, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_u_Rd_RnRm(_ARMINTR_UXTAB16 | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn), (_Rm)))
419 #define _arm_uxtah(_Rn, _Rm, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_u_Rd_RnRm(_ARMINTR_UXTAH | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn), (_Rm)))
420 
421 #define _arm_sxtb(_Rn, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_s_Rd_Rm(_ARMINTR_SXTB | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn)))
422 #define _arm_sxtb16(_Rn, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_s_Rd_Rm(_ARMINTR_SXTB16 | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn)))
423 #define _arm_sxth(_Rn, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_s_Rd_Rm(_ARMINTR_SXTH | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn)))
424 
425 #define _arm_uxtb(_Rn, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_u_Rd_Rm(_ARMINTR_UXTB | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn)))
426 #define _arm_uxtb16(_Rn, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_u_Rd_Rm(_ARMINTR_UXTB16 | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn)))
427 #define _arm_uxth(_Rn, _Rotation) (_ARMINTR_ASSERT_ROT(_Rotation), __arm_gen_u_Rd_Rm(_ARMINTR_UXTBH | _ARMINTR_ENCODE_XTROT(_Rotation), (_Rn)))
428 
429 #define _arm_pkhbt(_Rn, _Rm, _Lsl_imm) (_ARMINTR_ASSERT_RANGE((_Lsl_imm), 0, 31, "logical left shift"), \
430  __arm_gen_s_Rd_RnRm(_ARMINTR_PKHBT | _ARMINTR_ENCODE_PKHSHIFT(_Lsl_imm), (_Rn), (_Rm)))
431 #define _arm_pkhtb(_Rn, _Rm, _Asr_imm) (_ARMINTR_ASSERT_RANGE((_Asr_imm), 1, 32, "arithmetic right shift"), \
432  __arm_gen_s_Rd_RnRm(_ARMINTR_PKHTB | _ARMINTR_ENCODE_PKHSHIFT(_Asr_imm), (_Rn), (_Rm)))
433 
434 #define _arm_usad8(_Rn, _Rm) (__arm_gen_u_Rn_RmRs(_ARMINTR_USAD8, (_Rn), (_Rm)))
435 
436 #define _arm_usada8(_Rn, _Rm, _Ra) (__arm_gen_u_Rn_RmRsRd(_ARMINTR_USADA8, (_Rn), (_Rm), (_Ra)))
437 
438 #define _arm_ssat(_Sat_imm, _Rn, _Shift_type, _Shift_imm) (_ARMINTR_ASSERT_SAT_BIT((_Sat_imm), 1, 32), _ARMINTR_ASSERT_SAT_SHIFT((_Shift_type), (_Shift_imm)), \
439  _ARMINTR_S_DMx(_ARMINTR_SSAT | _ARMINTR_ENCODE_IMM5_16((_Sat_imm) - 1) | _ARMINTR_ENCODE_SAT_SH((_Shift_type), (_Shift_imm)), (_Rn)))
440 #define _arm_usat(_Sat_imm, _Rn, _Shift_type, _Shift_imm) (_ARMINTR_ASSERT_SAT_BIT((_Sat_imm), 0, 31), _ARMINTR_ASSERT_SAT_SHIFT((_Shift_type), (_Shift_imm)), \
441  _ARMINTR_S_DMx(_ARMINTR_USAT | _ARMINTR_ENCODE_IMM5_16(_Sat_imm) | _ARMINTR_ENCODE_SAT_SH((_Shift_type), (_Shift_imm)), (_Rn)))
442 
443 #define _arm_ssat16(_Sat_imm, _Rn) (_ARMINTR_ASSERT_SAT_BIT((_Sat_imm), 1, 16), \
444  _ARMINTR_S_DMx(_ARMINTR_SSAT16 | _ARMINTR_ENCODE_IMM4_16((_Sat_imm) - 1), (_Rn)))
445 #define _arm_usat16(_Sat_imm, _Rn) (_ARMINTR_ASSERT_SAT_BIT((_Sat_imm), 0, 15), \
446  _ARMINTR_S_DMx(_ARMINTR_USAT16 | _ARMINTR_ENCODE_IMM4_16(_Sat_imm), (_Rn)))
447 
448 #define _arm_rev(_Rm) (__arm_gen_u_Rd_Rm2(_ARMINTR_REV, (_Rm)))
449 #define _arm_rev16(_Rm) (__arm_gen_u_Rd_Rm2(_ARMINTR_REV16, (_Rm)))
450 #define _arm_revsh(_Rm) (__arm_gen_s_Rd_Rm2(_ARMINTR_REVSH, (_Rm)))
451 
452 #define _arm_smlad(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLAD, (_Rn), (_Rm), (_Ra)))
453 #define _arm_smladx(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLADX, (_Rn), (_Rm), (_Ra)))
454 #define _arm_smlsd(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLSD, (_Rn), (_Rm), (_Ra)))
455 #define _arm_smlsdx(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMLSDX, (_Rn), (_Rm), (_Ra)))
456 
457 #define _arm_smmla(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMMLA, (_Rn), (_Rm), (_Ra)))
458 #define _arm_smmlar(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMMLAR, (_Rn), (_Rm), (_Ra)))
459 #define _arm_smmls(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMMLS, (_Rn), (_Rm), (_Ra)))
460 #define _arm_smmlsr(_Rn, _Rm, _Ra) (__arm_gen_s_Rn_RmRsRd(_ARMINTR_SMMLSR, (_Rn), (_Rm), (_Ra)))
461 
462 #define _arm_smmul(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMMUL, (_Rn), (_Rm)))
463 #define _arm_smmulr(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMMULR, (_Rn), (_Rm)))
464 
465 #define _arm_smlald(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLALD, (_RdHiLo), (_Rn), (_Rm)))
466 #define _arm_smlaldx(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLALDX, (_RdHiLo), (_Rn), (_Rm)))
467 #define _arm_smlsld(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLSLD, (_RdHiLo), (_Rn), (_Rm)))
468 #define _arm_smlsldx(_RdHiLo, _Rn, _Rm) (__arm_gen_s_Rdn_RdnRmRs(_ARMINTR_SMLSLDX, (_RdHiLo), (_Rn), (_Rm)))
469 
470 #define _arm_smuad(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMUAD, (_Rn), (_Rm)))
471 #define _arm_smuadx(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMUADX, (_Rn), (_Rm)))
472 #define _arm_smusd(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMUSD, (_Rn), (_Rm)))
473 #define _arm_smusdx(_Rn, _Rm) (__arm_gen_s_Rn_RmRs(_ARMINTR_SMUSDX, (_Rn), (_Rm)))
474 
475 #define _arm_smull(_Rn, _Rm) (__arm_gen_s_Rdn_RmRs(_ARMINTR_SMULL, (_Rn), (_Rm)))
476 #define _arm_umull(_Rn, _Rm) (__arm_gen_u_Rdn_RmRs(_ARMINTR_UMULL, (_Rn), (_Rm)))
477 
478 #define _arm_umaal(_RdLo, _RdHi, _Rn, _Rm) (__arm_gen_u_Rdn_RdnRmRs(_ARMINTR_UMAAL, ((unsigned __int64)(_RdHi) << 32) | (_RdLo), (_Rn), (_Rm)))
479 
480 /* ARMv6T2 */
481 
482 #define _arm_bfc(_Rd, _Lsb, _Width) (_ARMINTR_ASSERT_RANGE((_Lsb), 0, 31, "least significant bit"), _ARMINTR_ASSERT_RANGE((_Width), 1, 32-(_Lsb), "width"), \
483  __arm_gen_u_Rd_Rd(_ARMINTR_BFC | _ARMINTR_ENCODE_IMM5_7(_Lsb) | _ARMINTR_ENCODE_IMM5_16((_Lsb) + (_Width) - 1), (_Rd)))
484 #define _arm_bfi(_Rd, _Rn, _Lsb, _Width) (_ARMINTR_ASSERT_RANGE((_Lsb), 0, 31, "least significant bit"), _ARMINTR_ASSERT_RANGE((_Width), 1, 32-(_Lsb), "width"), \
485  _ARMINTR_U_DDMx(_ARMINTR_BFI | _ARMINTR_ENCODE_IMM5_7(_Lsb) | _ARMINTR_ENCODE_IMM5_16((_Lsb) + (_Width) - 1), (_Rd), (_Rn)))
486 
487 #define _arm_rbit(_Rm) (__arm_gen_u_Rd_Rm2(_ARMINTR_RBIT, (_Rm)))
488 
489 #define _arm_sbfx(_Rn, _Lsb, _Width) (_ARMINTR_ASSERT_RANGE((_Lsb), 0, 31, "least significant bit"), _ARMINTR_ASSERT_RANGE((_Width), 1, 32-(_Lsb), "width"), \
490  _ARMINTR_S_DMx(_ARMINTR_SBFX | _ARMINTR_ENCODE_IMM5_7(_Lsb) | _ARMINTR_ENCODE_IMM5_16((_Width) - 1), (_Rn)))
491 #define _arm_ubfx(_Rn, _Lsb, _Width) (_ARMINTR_ASSERT_RANGE((_Lsb), 0, 31, "least significant bit"), _ARMINTR_ASSERT_RANGE((_Width), 1, 32-(_Lsb), "width"), \
492  _ARMINTR_U_DMx(_ARMINTR_UBFX | _ARMINTR_ENCODE_IMM5_7(_Lsb) | _ARMINTR_ENCODE_IMM5_16((_Width) - 1), (_Rn)))
493 
494 /* ARMv7 */
495 
496 #if defined (_M_THUMB)
497 
498 #define _arm_sdiv(_Rn, _Rm) (__arm_gen_s_Rd_RnRm(_ARMINTR_SDIV, (_Rn), (_Rm)))
499 #define _arm_udiv(_Rn, _Rm) (__arm_gen_u_Rd_RnRm(_ARMINTR_UDIV, (_Rn), (_Rm)))
500 
501 #endif /* defined (_M_THUMB) */
502 
504 {
508 }
510 
512 {
516 }
518 
519 void __cps(unsigned int _Ops, unsigned int _Flags, unsigned int _Mode);
520 
521 
523 {
532 }
534 
535 void __dmb(unsigned int _Type);
536 void __dsb(unsigned int _Type);
537 void __isb(unsigned int _Type);
538 
539 /* ARMv7VE */
540 
542 {
591 }
593 
594 void _WriteBankedReg(int _Value, int _Reg);
595 int _ReadBankedReg(int _Reg);
596 
597 #ifdef __cplusplus
598 }
599 #endif /* __cplusplus */
Definition: armintr.h:506
Definition: armintr.h:586
Definition: armintr.h:585
Definition: armintr.h:554
Definition: armintr.h:568
Definition: armintr.h:551
Definition: armintr.h:529
Definition: armintr.h:548
int __arm_gen_s_Rd_Rn_q(const unsigned int, int)
Definition: armintr.h:579
Definition: armintr.h:546
int __arm_gen_s_Rd_Rd(const unsigned int, int)
int __arm_gen_s_Rd_Rm_q(const unsigned int, int)
unsigned int __arm_gen_u_Rd_RnRm_g(const unsigned int, unsigned int, unsigned int)
Definition: armintr.h:560
int __arm_gen_s_Rn_RmRs(const unsigned int, int, int)
Definition: armintr.h:584
Definition: armintr.h:26
Definition: armintr.h:559
unsigned int __arm_gen_u_Rd_Rn(const unsigned int, unsigned int)
Definition: armintr.h:530
Definition: armintr.h:590
_tag_ARMINTR_CPS_FLAG
Definition: armintr.h:511
Definition: armintr.h:563
Definition: armintr.h:528
enum _tag_ARMINTR_CPS_OP _ARMINTR_CPS_OP
__int64 __arm_gen_s_Rdn_RmRs(const unsigned int, int, int)
void _WriteBankedReg(int _Value, int _Reg)
Definition: armintr.h:581
unsigned int __arm_gen_u_Rd_RdRm(const unsigned int, unsigned int, unsigned int)
enum _tag_ARMINTR_CPS_FLAG _ARMINTR_CPS_FLAG
Definition: armintr.h:505
int __arm_gen_s_Rd_RdRn(const unsigned int, int, int)
Definition: armintr.h:550
Definition: armintr.h:588
enum _tag_ARMINTR_BARRIER_TYPE _ARMINTR_BARRIER_TYPE
Definition: armintr.h:514
Definition: armintr.h:524
_tag_ARMINTR_BARRIER_TYPE
Definition: armintr.h:522
int __arm_gen_s_Rd_RnRm_g(const unsigned int, int, int)
Definition: armintr.h:513
Definition: armintr.h:570
Definition: armintr.h:29
Definition: armintr.h:544
Definition: armintr.h:583
Definition: armintr.h:558
unsigned __int64 __arm_gen_u_Rdn_RmRs(const unsigned int, unsigned int, unsigned int)
Definition: armintr.h:555
Definition: armintr.h:552
Definition: armintr.h:545
int __arm_gen_s_Rd_Rm(const unsigned int, int)
Definition: armintr.h:569
int __arm_gen_s_Rd_RnRm_q(const unsigned int, int, int)
Definition: armintr.h:573
Definition: armintr.h:589
unsigned int __arm_gen_u_Rd_RnRm(const unsigned int, unsigned int, unsigned int)
enum _tag_ARMINTR_SHIFT_T _ARMINTR_SHIFT_T
Definition: armintr.h:515
__int64 __arm_gen_s_Rdn_RdnRmRs(const unsigned int, __int64, int, int)
Definition: armintr.h:566
Definition: armintr.h:571
Definition: armintr.h:564
Definition: armintr.h:576
Definition: armintr.h:527
Definition: armintr.h:572
Definition: armintr.h:28
_tag_ARMINTR_SHIFT_T
Definition: armintr.h:24
Definition: armintr.h:525
Definition: armintr.h:547
Definition: armintr.h:575
Definition: armintr.h:565
unsigned int __arm_gen_u_Rd_Rm(const unsigned int, unsigned int)
Definition: armintr.h:531
unsigned __int64 __arm_gen_u_Rdn_RdnRmRs(const unsigned int, unsigned __int64, unsigned int, unsigned int)
Definition: armintr.h:580
Definition: armintr.h:577
int __arm_gen_s_Rn_RmRsRd(const unsigned int, int, int, int)
unsigned int __arm_gen_u_Rd_Rd(const unsigned int, unsigned int)
void __isb(unsigned int _Type)
void __dsb(unsigned int _Type)
void __dmb(unsigned int _Type)
int __arm_gen_s_Rd_Rm2(const unsigned int, int)
Definition: armintr.h:567
enum _tag_ARMINTR_BANKED_REG _ARMINTR_BANKED_REG
void __cps(unsigned int _Ops, unsigned int _Flags, unsigned int _Mode)
Definition: armintr.h:556
Definition: armintr.h:587
Definition: armintr.h:557
_tag_ARMINTR_CPS_OP
Definition: armintr.h:503
unsigned int __arm_gen_u_Rn_RmRs(const unsigned int, unsigned int, unsigned int)
Definition: armintr.h:574
Definition: armintr.h:578
unsigned int __arm_gen_u_Rd_Rm2(const unsigned int, unsigned int)
Definition: armintr.h:553
int __arm_gen_s_Rd_Rn(const unsigned int, int)
Definition: armintr.h:543
int __arm_gen_s_Rd_RnRm(const unsigned int, int, int)
Definition: armintr.h:549
Definition: armintr.h:526
Definition: armintr.h:561
unsigned int __arm_gen_u_Rn_RmRsRd(const unsigned int, unsigned int, unsigned int, unsigned int)
_In_ int _Value
Definition: setjmp.h:173
Definition: armintr.h:507
_tag_ARMINTR_BANKED_REG
Definition: armintr.h:541
Definition: armintr.h:582
unsigned int __arm_gen_u_Rd_RdRn(const unsigned int, unsigned int, unsigned int)
int _ReadBankedReg(int _Reg)
Definition: armintr.h:562
int __arm_gen_s_Rd_RdRm(const unsigned int, int, int)
Definition: armintr.h:27